“Trains need to transmit a large amount of equipment control and passenger service information. With the continuous growth of the quantity and types of these information, a large-capacity, high-speed information transmission system is urgently needed. To this end, the International Electrotechnical Commission (IEC) has developed a standard for regulating the data communication of on-board equipment – IEC61375 (train communication network standard), namely the TCN standard, which became an international standard in June 1999.At present, the main TCN product suppliers in the world are Germany’s Siemens and Switzerland’s Duagon. Domestic Zhuzhou Electric Locomotive Research Institute and Dalian CNR Electric Traction Research Institute have conducted a large number of TCN-related researches.
Trains need to transmit a large amount of equipment control and passenger service information. With the continuous growth of the quantity and types of these information, a large-capacity, high-speed information transmission system is urgently needed. To this end, the International Electrotechnical Commission (IEC) has developed a standard for regulating the data communication of on-board equipment – IEC61375 (train communication network standard), namely the TCN standard, which became an international standard in June 1999. At present, the main international suppliers of TCN products are Siemens of Germany and Duagon of Switzerland. The domestic Zhuzhou Electric Locomotive Research Institute and Dalian CNR Electric Traction Research Institute have carried out a lot of TCN-related research work and have achieved fruitful scientific research results. .
The TCN standard recommends using the twisted-wire train bus WTB on the upper layer of the locomotive and the multi-purpose vehicle bus MVB on the lower layer. The MVB bus is connected with various electrical devices in the locomotive. These devices can be divided into 5 categories according to their performance. The main feature of the second category of devices is that they have the function of message data communication. In order to realize message data communication, it is necessary to adopt software programming under the support of real-time operating system, and use interfaces such as application programming interface API to call various functions of network protocols, so as to realize the communication of message data. The hardware core of MVB 2 equipment adopts the ARM7 core microprocessor NET+50 as the main CPU to realize the overall control of the system, and the MVBC01 chip is used as the MVB communication controller to realize the data processing of the link layer. The software core adopts the embedded real-time operating system Nucleus Plus To achieve task management, interrupt management and other upper management.
2. Hardware design of MVB type 2 equipment system
The hardware system design mainly includes the design of application processor module, communication memory module, communication controller module, memory module, PC104 interface module, physical layer interface module, etc. The core modules are ARM processor and MVB communication controller MVBC01. The block diagram of the system hardware design is shown in Figure 1.
The functions and design methods of each part of the system hardware circuit are as follows:
2.1 Application Processor Module
The application processor adopts ARM core microprocessor NET+50 as the core processor. The NET ten 50 is produced by Netsilicon and belongs to the ARM7 series. NET+50 processor includes an ARM7TDMI core, 32-bit internal bus, supports all SRAM, SDRAM, FLASH, E2PROM, has 40 programmable I/O interface pins, 16 input interface pins, 36 programmable interrupts, 2 completely independent HDLC/UART/SPI serial ports and a complete Ethernet controller.
2.2 Memory modules
The memory module provides the required program storage space, memory space and data storage space for the ARM processor NET+50 to work normally. NET+50 integrates the Memory Controller Module (Memory Controller Module) to provide seamless connection for storage devices. The system implements the signals and logic for accessing the corresponding memory by configuring the memory controller module’s control register and chip select CS control register. .
In this design, high-speed SDRAM with a size of 16 MB is selected to provide memory services for the system, NVRAM with a size of 512 kB is selected to provide data storage space for the system, and FLASH with a size of 4 MB is selected to provide program storage space for the system. Use the address line, data line and corresponding chip select, read/write, clock line of ARM processor to complete the addressing of the memory.
2.3 Communication Controller Module
The communication controller MVBC is a new generation core processor on the MVB bus. It is independent of the physical layer and functional devices. It provides communication interfaces and communication services for each device on the bus. , 3 and 4 types of equipment. MVBC converts the serialized signal from the MVB bus into parallel data bytes, and also sends the bytes to be sent to the transmission medium by the serialization circuit. MVBC can realize the data processing of the data link layer and a part of the transport layer, and interact with the upper layer software through the communication memory.
The MVB communication controller in this system adopts the MVBC01 ASIC special-purpose chip, which conforms to the IEC61375-1 international standard. The MVBC01 dedicated chip adopts a 16-bit data bus, provides a wealth of interface control signals, simplifies the interface design with various host CPUs and communication memories, and supports the functions of the link layer and below in the MVB protocol.
2.4 Communication Memory Module
The communication memory address space saves all the data and information of the MVBC01, which can be accessed by the MVBC01 and by the ARM processor. In this system, two SRAM cy62148s with a size of 512 kB are used to expand the addressing space of 1 MB. The addressing space of the communication memory is divided into 4 parts, namely Logical AddreSS Space (LA), Device AddressSpace (DA), Service Area (1 kB) and Miscellany.
The communication memory is connected with the ARM processor and MVBC01 through the data line and the address line respectively, so as to realize data exchange and address addressing. The connection diagram of the ARM processor, MVBC01 and the communication memory is shown in Figure 2.
The MVBC01 integrates the Traffic Memory Controller (TMC) module, which is responsible for controlling the access mode of the communication memory. The TMC is closely related to the arbitration controller and logical address. The TMC module is responsible for controlling three memory access modes, namely: ARM CPU accesses communication memory; ARM CPU accesses MVBC internal registers; MVBC01 accesses communication memory. The TMC module also arbitrates the access conflicts caused by the simultaneous access of the ARM processor and the MVBC to the communication memory.
2.5 MVB physical layer interface circuit module
The design of the physical layer interface circuit module is shown in Figure 3. The physical layer interface adopts electrical short-distance medium ESD+ interface, the system signal channel uses optocoupler to achieve electrical isolation between the main system and the outside world to improve system reliability, uses RS 485 chip as a transceiver, and uses an overvoltage protection module to prevent transient damage to the device.
The MVBC ports ICA (MVB Input Data Channel A) and ICB (MVB Input Data Channel B) shown in Figure 3 are MVB input data channel A and input data channel B, respectively, and the MVB signal from the physical layer transceiver is this port It is sent to the MVB communication controller MVBC01; the MVBC port OC (MVB Output Data Channel) is the MVB data output port, through which the data will be sent to the physical layer transceiver; the MVBC port SF (Send Frame) is the output port, and the output signal can be As the enable signal of the physical layer, when this signal is valid, it indicates that a packet is being output through the MVBC port OC (MVB Output Data Channel).
When the MVB equipment is running normally, the program monitoring and debugging can be carried out through the RS 485/RS 232 communication interface. The system can choose whether the RS 485/RS 232 interface works under RS 485 or RS 232 through the jumper.
There are other modules such as watchdog, JTAG interface, clock, power supply, PC104 interface, etc., which will not be described in detail in this article.
3. System software design
3.1 System Software Architecture
The software system of MVB type 2 equipment adopts a typical embedded software architecture, including driver layer, operating system layer, and application software layer, among which the operating system layer is the core of the software system. The software structure of the system is shown in Figure 4.
The functions of each part of the system software structure are as follows:
3.1.1 Driver Layer
The driver layer is a layer directly related to the hardware, which provides the required driver support for the operating system and applications. This layer mainly includes 3 types of programs: board-level support BSP, system-level driver and application-level driver.
Board-level support for BSP Before the user’s application program starts, there must be a special start-up code to complete the initialization of the system, that is, board-level support for BSP. The board-level support BSP is between the physical hardware and the real-time operating system. After the system is powered on, it initializes the hardware environment of the system, including initializing the ARM processor, initializing the interrupt controller, initializing the memory, and initializing the stack. The BSP initialization program flow of NucleusPlus operating system is shown in Figure 5.
System-level drivers are drivers related to system software. Such drivers are drivers required by system software such as operating systems and middleware. Their development should be carried out according to the requirements of system software.
Application-level drivers are application-related drivers, independent of the operating system, and determined by the application.
3.1.2 Operating system layer
The operating system layer is the core of embedded software and is the software support platform of the system. It mainly includes real-time operating system kernel, file system, power management, embedded GUI system, and embedded network system. The embedded kernel is the basic and necessary part, which mainly completes functions such as task scheduling, memory management, inter-task communication, task synchronization and mutual exclusion, interrupt management, and timers. The system adopts Nucleus Plus embedded operating system, which can fully meet the requirements of MVB for real-time, reliability, integrity and effectiveness. NucleusPlus adopts the method of software components, each component has a single and clear purpose, including 16 components such as task control management, memory control management, timer management, interrupt, system diagnosis, and I/O driver management.
3.1.3 Application software layer
The application software layer is mainly composed of a plurality of relatively independent application tasks, and each application completes a specific job, which mainly includes the MVB protocol stack software. With the support of the real-time operating system kernel, the MVB protocol stack software completes the MVB network data communication task through the MVB driver module. User applications can use the interface functions of the MVB protocol stack to access the required data sets, and use the received or sent data to perform corresponding control or other data processing work.
3.2 Real-time protocol
Each network must have its corresponding network software running on it, these software are called protocols. The protocol running on the Internet is called TCP/IP protocol, and the protocol similar to TCP/IP running on the train communication network is called Real Time Protocol (RTP). The real time protocol is one application and another application. Communication on the train communication network provides protocols and services.
The real-time protocol layered structure is shown in Figure 6. It can be known from the hierarchical structure in the figure that the MVB real-time protocol includes two parts: process variable communication and message data communication. It can be seen from the figure that the protocols and services of the variables include the process data link layer interface (LPI) and the application layer interface (AVI) of the variables. Message protocols and services include Message Data Link Layer Interface (LMI), Network Layer, Transport Layer, Session Layer, and Application Layer Interface (AMI). The link layer interface is also called the low-level interface, which specifies the services from the bus, and the application layer interface is also called the high-level interface, which specifies the application layer interface provided to the application.
3.3 Message Communication Mechanism and Its Implementation
The main feature of MVB 2 type equipment is to realize the sending and receiving of message data. The real-time protocol in message communication is executed by the messenger, which runs in parallel with the application as an independent process. The network layer, transport layer, session layer and presentation layer of the real-time protocol are executed and implemented by the messenger. The messenger and the application layer have a message application layer interface (AMI), through which the application can call the service of the messenger. At the same time, the messenger and the link layer also have an interface: the message link layer interface (LMI), and the link layer provides services to the messenger through this interface. When implementing message communication programmatically, you only need to use the message application layer interface.
When a user develops a program to realize message communication, it is to use the interface functions in the message application layer interface to call various functions of the messenger. The application program for realizing message communication is written and executed in this order. The flow of the realization program of the message data is shown in FIG. 7 .
The use of products that conform to the TCN standard is an important development trend in the development of the next generation of new trains. Based on the research on the IEC61375-1 train communication network standard, this paper proposes a design scheme for the software and hardware of MVB 2 equipment and completes the design of each functional module of the system hardware. And part of the design of the upper software, the MVB real-time protocol RTP and the mechanism of message communication have also been deeply studied, and the programming implementation method of message communication has been given. Through the in-depth research and functional design and realization of MVB 2 equipment based on ARM processor, it not only accumulates experience for developing higher category MVB equipment in the future, but also provides reference for further independent development of other MVB products that meet the TCN standard.