Imperas announces RISC-V product updates

Imperas announces RISC-V product updates

Imperas announces RISC-V product updates

Imperas Software, an expert in RISC-V processor simulation and verification technology, has announced its latest product updates as a general release to all customers and users.

Offered as freely available, open-source reference models for the RISC-V community and as commercial products, they now support the latest ratified extensions: Bit Manipulation, Cryptographic (scalar), and Vector, plus the Privilege Specification enhancements.

These latest additions extend the range of RISC-V projects based on the open standard RISC-V ISA (Instruction Set Architecture) targeted at optimised solutions in applications that range from microcontrollers and application processors, through to multicore arrays for AI (Artificial Intelligence), Machine Learning, and HPC (High Performance Computing).

Imperas products and tools are supported with open-source processor and platform models licensed under Apache 2.0 via the Open Virtual Platforms initiative and available at OVPworld.org. These models and platforms can be modified and further extended as required.

The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP application programming interfaces (APIs). The full range of 300+ processor models is based on over 12 ISAs to support heterogeneous designs or for projects migrating other architectures to RISC-V.

The Imperas RISC-V reference models are used for design verification (DV) of RISC-V processors and for virtual platforms/prototypes to support software development and test throughout the design cycle.

The RISC-V community is supported with multiple free-to-use options, including riscvOVPsim, riscvOVPsimPlus, and riscvOVPsimCOREV. In addition, the Imperas commercial solutions are available with professional support plus extra features for more complex designs.

They can be integrated within other standard EDA environments, such as SystemC, SystemVerilog, and well-known simulation and emulation tools from Cadence, Siemens EDA, and Synopsys, plus the cloud-based simulation offering from Metrics Technologies.

“An ISA specification is probably the most important interface in computer science; it defines the boundary between the software programme and the underlying hardware,” said Simon Davidmann, CEO, Imperas Software. “RISC-V is the first broadly adopted open standard ISA with many independent implementations.

“Unlike the single-source developments of the past, RISC-V is community-based with both open-source and proprietary commercial supporters. We are pleased to announce that the Imperas simulation technology and models are ready to support the fully ratified specifications, plus all the major previous revisions as we continue to support our users.”