On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

This application note discusses on-chip oversampling in successive approximation register (SAR) type analog-to-digital converters (ADCs). There are two common oversampling techniques: normal averaging and rolling average. These techniques are implemented in the AD7380/AD7381 and its family of high-throughput SAR ADCs, so that the average conversion data is directly available and the burden on the digital controller is reduced, which is an advantage in data acquisition systems.

By: Jonathan Colao, Analog Devices

Introduction

This application note discusses on-chip oversampling in successive approximation register (SAR) type analog-to-digital converters (ADCs). There are two common oversampling techniques: normal averaging and rolling average. These techniques are implemented in the AD7380/AD7381 and its family of high-throughput SAR ADCs, so that the average conversion data is directly available and the burden on the digital controller is reduced, which is an advantage in data acquisition systems.

In precision data acquisition systems, the higher the signal-to-noise ratio (SNR) and the effective number of bits (ENOB), the better the system can measure the signal in the presence of broadband noise.

Noise can degrade system performance. Ways to reduce noise include replacing the system with a higher resolution ADC such as a sigma-delta ADC or SAR ADC, or oversampling and using digital filtering techniques.

Oversampling techniques have a long history in the design of sigma-delta ADC architectures. A sigma-delta ADC consists of a sigma modulator followed by a digital signal algorithm block (or digital filter). Sigma modulators can be as small as one-bit quantizers to collect thousands of samples, which are then decimate to achieve high-resolution conversion results. The more samples involved in averaging, the higher the resolution that can be obtained, and thus the closer the conversion result is to the sampled value. Common sigma-delta applications are temperature monitoring and scale measurement systems.

The sigma-delta ADC architecture relies on sampling smaller charges at a rate much higher than the bandwidth of interest. It takes more samples but a smaller charge per acquisition. The oversampling range of a typical sigma-delta ADC is between 32x and 1000x the signal of interest. The result of oversampling combined with noise shaping (modulation scheme) moves the in-band noise outside the bandwidth of interest. Noise moved to higher bandwidths is then filtered out by digital filtering. The result is lower noise and higher resolution in the bandwidth of interest. Each conversion result of a sigma-delta ADC results from smaller but more frequent sampling events.

The SAR ADC uses successive approximation to determine the result. SAR ADCs use a step-by-step approach to determine what each bit of the digital representation is at a single sampling instant. SAR sampling charge redistribution capacitor and digital-to-analog converter (DAC) array. The sampled data is compared to each binary weighted capacitor array. The total number of binary weighted capacitors determines the number of bits or resolution of the SAR ADC. The conversion process is controlled by a high-speed internal clock and an array of capacitive DACs, capable of rapidly converting changing signals. SAR ADCs are used in data acquisition systems that require wide bandwidth.

SAR ADCs typically convert a single moment in time to provide a digital answer related to a specific moment in time. The use of oversampling has increased with the advent of faster SAR converters in order to improve the resolution of critical target bandwidths. In today’s SAR ADCs that use oversampling techniques, this technique is often performed by post-processing on a microcontroller or field programmable gate array (FPGA). Analog Devices has built-in oversampling into its SAR ADC family. This oversampling feature improves noise performance, simplifies interface requirements, and allows the user to use it directly without having to design an FPGA or microcontroller and perform resource-intensive averaging. The oversampling feature also maximizes data processing performance at manageable data rates.

Table 1. Analog Devices Dual-Channel, Simultaneously Sampling SAR ADC Family

Iinput type

16 bit

14 bit

12 bits

difference

AD7380

AD7381

single ended

AD7386

AD7387

AD7388

oversampling

During analog-to-digital conversion, the analog signal is digitized by the ADC. Compared to non-oversampling solutions, oversampling increases the effective resolution of a digitized signal by sampling an analog signal and digitizing that signal at a much higher rate than required. Oversampling allows the user to average converter noise over a wider bandwidth, thereby eliminating noise. For uncorrelated, broadband (white) and zero (0) mean noise, when averaged and/or filtered to a specific bandwidth, the noise is reduced by a factor of √2 or 3 dB for every 2x oversampling. Other spectral content, such as correlated noise or harmonics, is not degraded by averaging. Figure 1 shows the noise level (dark gray) of an ADC from multiple sources, including quantization noise, thermal noise, and external noise (such as drivers, clocks, and references), distributed over the Nyquist bandwidth.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 1. Average filtered noise

According to Nyquist theory (fSAMPLING ≥ (2 × fIN)), in order to accurately reconstruct the signal, the input signal must be sampled at a rate at least twice the target maximum frequency. The same criteria are followed for oversampling to occur. Oversampling reduces the noise of the signal, resulting in an increase in the SNR of the system and thus an increase in resolution (assuming no significant distortion components).

Oversampling is a digital signal processing technique in which samples are taken and averaged. The data samples are averaged like a low pass filter.

Analog Devices’ AD7380 family is a family of simultaneous sampling SAR ADCs capable of on-chip oversampling. This family of SAR ADCs can perform two oversampling techniques: normal averaging and rolling averaging.

Normal Average Oversampling

In normal averaging oversampling, the averaging algorithm is implemented as simple averaging: add M samples together, and divide the resulting sum by M. In this approach, a new set of M samples is collected for each averaged result.

Table 2 gives a general representation of how the algorithm works. In this example, the data has 12 samples. When M = 2, the number of samples participating in the averaging is 2, and a new output is produced every two samples, so the rate is half the effective sampling rate. The result is the average of sample 1 and sample 2, sample 3 and sample 4, and so on.

Table 2. Normal Average Example

Number of samples

Sampling results

Average result

M = 2

M = 4

1

0.200

0.2500

0.2400

2

0.300

3

0.230

0.2350

4

0.240

5

0.260

0.2300

0.2500

6

0.200

7

0.240

0.2700

8

0.300

9

0.270

0.2600

0.2450

10

0.240

11

0.250

0.2300

12

0.210

Similarly, when applying the averaging factor M = 4, the first set of four samples is averaged, then the next set of four samples (samples 5 to 8) are averaged. The simplified normal mean formula is:

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

in:

is the average of M samples.

M is the number of samples participating in the averaging.

Siis the nth sample value.

In the AD7380 SAR ADC family, normal averaging oversampling is implemented on-chip and up to 32 averaging samples can be collected. As long as this technique is enabled, the AD7380 will automatically acquire M conversion samples and output the average conversion result. The availability of the conversion result depends on the acquired M samples, which are set by the oversampling rate of the OSR bits in the CONFIGURATION1 register of the AD7380 family. When the conversion of M samples is complete, the result can be read.

Figure 2 shows how the AD7380 performs this algorithm. This example assumes M = 8, which is an oversampling ratio (OSR) of 8, so eight samples are collected and averaged. When a conversion is initiated internally, the AD7380 performs a series of conversions and acquisitions until the desired number of samples (M) is completed. Then, perform averaging on the captured data. This process introduces a certain processing delay, as shown in Figure 2. The averaged result is obtained at T1 and output on the SDOx pin. At this point, a new averaging operation begins, resulting in a new conversion burst to take M more samples. Figure 2 shows that applying this technique reduces the effective ODR of the sampling system. The decrease in ODR is inversely proportional to the sample size (M) or the increase in OSR. For applications that require better performance but accept slower ODR, the normal average oversampling method is recommended.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 2. Normal Average Oversampling Operation

rolling average oversampling

The rolling average oversampling technique uses a buffer to store samples to perform the averaging process. The rolling average algorithm selects the latest M samples stored in the buffer and divides the resulting sum by M. In digital designs, buffers require additional space to create additional storage areas. In the rolling average oversampling technique, the buffer storage capacity of the small ADC is limited, and a first-in, first-out (FIFO) algorithm is used. When the buffer is full and new samples are available, the oldest data in the buffer is discarded, as shown in Figure 3. Using the sampled data from the previous example, the first eight sampled results fill the FIFO buffer (S1 to S8). When new sample data appears (S9), S1 is removed from the buffer and S9 is inserted into the buffer. This process is repeated as new samples are stored in the buffer.

As mentioned earlier, the rolling average oversampling technique adds the latest M samples and divides the sum by M to calculate the average. In the example shown in Figure 3, M = 4, the algorithm adds the four samples B1 to B4 in the FIFO buffer (which are the latest four samples) and divides by 4. During the next averaging, the same FIFO buffer locations participate in averaging, but the contents of these buffers change. In the case of M = 8, all samples in the FIFO buffer are included in the sum operation and then divided by 8.

To enable rolling average oversampling in the AD7380 family, the OS_MODE bit must be set to logic 1 and the OSR bit of the CONFIGURATION1 register must be a valid non-zero value to store up to 8 samples in the FIFO buffer. The FIFO buffer will be updated immediately after the conversion occurs. With rolling average oversampling enabled, its algorithm collects the latest M samples from the FIFO buffer and divides it by M, where M is the OSR. The averaged result is then output on the SDOx pin of the AD7380.

Figure 4 shows that as long as there are the required number of samples in the buffer (M = 8 in this example), subsequent conversion cycles will provide oversampling results. Therefore, the output data rate (ODR) will be faster, even if M (number of samples) increases. The rolling average oversampling technique is useful in applications that require high ODR and high performance. The performance gains that can be achieved with this technique are limited by the available buffer storage space. The simplified rolling average formula is:

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

in:

is the average of M samples.

M is the number of samples participating in the averaging.

BiSamples for a specific buffer location.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 3. Example of rolling average oversampling buffer

,On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 4. Rolling Average Oversampling Operation

Advantages of oversampling

improve noise

With oversampling, the ADC can achieve higher dynamic range. Oversampling works by assuming that the noise sources are uncorrelated and have zero mean, this is because samples treat white noise as uniformly distributed in the spectrum, or a Gaussian noise distribution centered on adjacent codes that can be averaged. reduced signal.

Figure 5 is an example of a fast Fourier transform (FFT) curve generated using the AD7380 for two cases: no oversampling and with rolling average oversampling applied, OSR = 8.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 5. Noise Improvement Using the AD7380

As can be seen, there is a significant improvement in the noise floor, which is consistent with the increase in SNR (see Figure 6). In this example, with normal average oversampling and rolling average oversampling enabled, the SNR improves to 96 dB and 95 dB, respectively.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 6. AD7380 SNR vs. Oversampling Ratio

To evaluate the SNR improvement obtained by applying the oversampling technique, use the following formula:

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

in:

N is the ADC resolution.

fs is the sampling frequency.

BW is the target bandwidth.

10log(fS/(2 × BW)) is the process gain.

fS/(2 × BW) is the sampling ratio or Nyquist ratio.

Note that the processing gain is included to account for the additional oversampling process of sampling beyond 2 × BW. In the following equation, increasing the sampling frequency by a factor of k (where k is the number of samples participating in averaging or the oversampling rate) results in an increase in SNR.

Oversampling = k × (fS/(2 × BW))

Ideally, doubling the value of k increases SNR by 3 dB.

Tables 3 and 4 detail the effect of typical normal and rolling average oversampling on SNR at different oversampling rates. As the oversampling rate increases, the SNR also increases.

Table 3. Typical SNR Performance for AD7380 Normal Average Oversampling

oversampling rate

SNR (dB)

Output Data Rate (kSPS)

Reference voltage (VREF) = 2.5 V

VREF = 3.3V

disabled

16×

32×

90.8

92.6

94.3

95.8

96.3

96.5

92.5

94

95.4

96.3

96.8

97

4000

1500

750

375

187.5

93.75

Table 4. Typical SNR Performance for AD7380 Rolling Average Oversampling

oversampling rate

SNR (dB)

Output Data Rate (kSPS)

disabled

90.3

91.7

93.37

94.66

4000

4000

4000

4000

Both averaging techniques are available in the AD7380 family. Each technology is suitable for a range of applications. However, each technology has its own characteristics that must be considered for specific applications. The normal average oversampling technique has the following characteristics:

• Better performance because this technique samples the extra data for averaging.

• The ODR is slower because the sample count or OSR increases, allowing the application to use a lower SCLK frequency, thereby reducing the overall cost.

• The signal bandwidth is significantly smaller than the slew rate (see Figure 7). Note that the bandwidth limit is similar to an effective low-pass filter.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 7. SNR vs. Input Frequency, Oversampling Frequency Response

The rolling average oversampling technique has the following characteristics:

• The sampling rate can be varied and controlled by the application via pins.

Ÿ Fast sampling rate up to 4 MSPS.

Ÿ Due to buffer limitations, the number of samples participating in the averaging is limited to 8.

• Wider signal bandwidth (see Figure 7).

Higher resolution (N)

As mentioned earlier, both oversampling techniques can significantly improve performance. Using the following formula, the SNR is limited by the N resolution of the ADC.

Calculate N using the following formula:

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Given an ideal 16-bit ADC, calculating the SNR, the maximum achievable SNR is 98 dB.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

The maximum improvement in SNR is limited by the number of ADC bits, and as shown in Figure 6, there is little improvement in SNR performance when the oversampling ratio is greater than 8. To gain the benefits of oversampling, the N resolution must be increased, which is the significance of the AD7380’s resolution-boosting feature.

increase resolution

Even with limitations, the AD7380 family can effectively increase the resolution through oversampling, thereby extending the achievable SNR. To enable the on-chip boosted resolution feature, write to the RES bit (bit 2) of the CONFIGRATION1 register.

To see how oversampling improves SNR, use the previous formula to calculate the SNR of a 17-bit ADC. The result is an SNR of 104.1 dB.

Substituting this value into the SNR formula yields the oversampling factor k required to increase the resolution by 1 bit.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

To increase the resolution by 1 bit, the ADC oversampling ratio must be at least 4. The following formula is the calculation formula of the oversampling coefficient required to improve the resolution:

oversampling = 4x × (fS/(2 × BW))

where x is the extra resolution. Table 5 summarizes the resolution improvement at different oversampling rates.

Table 5. Resolution improvement at different oversampling rates

oversampling rate

increase in digits

0.5

1

1.5

16×

2

32×

2.5

Figure 8 shows the SNR performance of the AD7380 with the resolution boost feature enabled. The achieved SNR performance exceeds 100 dB. An additional 2-bit resolution boost improves quantization noise, resulting in improved SNR. Resolution boosting is a way to increase the dynamic range of a system without the added cost of 2-bit resolution. The disadvantage of this feature is that the serial port interface (SPI) SCLK needs to provide an additional 2 clock cycles to output the average conversion result.

On-Chip Oversampling of Analog Devices AD7380 Family of SAR ADCs

Figure 8. SNR vs. Oversampling Ratio with AD7380 Resolution Boosting Feature Enabled

Application example

Motor control applications utilize optical encoders to accurately measure position. For example, the sine and cosine outputs of the encoder are interpolated and must be captured at the same time. For such applications, a simultaneous sampling SAR ADC such as the high throughput AD7380 is recommended. The angular position θ is obtained from the arctangent of the captured sine and cosine signals. When these signals are ideal, the results are accurate. In practical applications, these signals can be affected by noise, resulting in erroneous readings. These deviations lead to errors in the angular position of the encoder.

An example where high encoder accuracy is required is when the motor is running at a lower speed, i.e. the motor starts to decelerate and then reaches the target position. The sine and cosine signals are digitally filtered using the AD7380’s on-chip oversampling technique to achieve high dynamic range. Enhanced sine and cosine transformations result in higher angular position accuracy, which is required in many applications such as pick and place machines for mounting miniature components to printed circuit boards (PCBs), or in industrial machinery for transporting and moving loads the robotic arm to a specific location.

in conclusion

Oversampling is a data processing technique that enables an ADC to provide accurate conversion results. SAR ADCs have used this technique in the past in post-processing via microcontrollers, DSPs, or FPGAs. ADI’s family of high-speed SAR ADCs, such as the AD7380, have integrated this functionality into two on-chip oversampling techniques, normal averaging and rolling averaging. Average conversion results can be obtained directly and quickly through the SDOx pin, with significant results and are immediately reflected in ADC parameters such as SNR and full dynamic range.

The normal average oversampling technique is suitable for applications that require higher performance and can accept lower clock speeds and output data rates. The rolling average oversampling technique is suitable for applications that require speed and performance.

Increasing the resolution further improves oversampling performance. Note that combining the two oversampling techniques discussed, an additional 2 bits of resolution can be added directly using the resolution boosting feature of the AD7380 family. The AD7380 series are high-speed SAR ADCs that offload the SPI on the microcontroller to allow for additional data processing. The AD7380 family of devices is highly reliable and improves ADC conversion accuracy.

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